design of a fuzzy controller chip with new structure, supporting rational-powered membership functions

in this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. the maximum output delay for general fuzzy logic controllers (flc) is about 86 ns corresponding to 11.63 mflips (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 mflips. this mixed analog/digital realization of the circuit makes the design programmable and extendable. the proposed controller supports rational-power membership functions with a resolution of 0.03125. simulation results of the controller using hspice simulator level 49 in 0.35um in cmos process technology (bsim3v3) show an average power consumption of 4.38mw, and an rms error of 1.26%. this controller can be used in many applications in which there is a need for a controller chip by correct programming with system experts. meanwhile the whole area of the chip is 0.0775mm2.